The chip landscape

Annex B. Data sources and limitations

Data sources

The analyses in this paper build on highly disaggregated data at the level of the semiconductor fab sourced from two commercial data providers, SEMI and TechInsights Inc., and complemented with desk research.

SEMI’s World Fab Watch

SEMI is a global industry association that also offers a variety of commercial datasets, mainly focusing on the supplier markets, such as semiconductor manufacturing equipment and materials. Their World Fab Watch (WFW) is a quarterly updated dataset of all wafer fabrication facilities globally (SEMI, 2025[6]). WFW provides comprehensive information about the location, volume, technical capabilities and planned expansions (capital expenditures) per fab. The analyses presented here are based on SEMI’s 2025 third quarter reporting of the WFW dataset.

TechInsights’ 300mm Watch and Semico Fab Database

The 300mm Watch from TechInsights provides similar information to SEMI’s WFW but focuses only on fabs that process 300mm wafers (TechInsights, 2024[8]). While today’s advanced logic and memory fabs are all using 300mm wafers, compound semiconductors, such as gallium-nitride (GaN) and silicon-carbide (SiC) are just transitioning from 150mm to 200mm wafer fabrication. Therefore, TechInsights’ data need to be complemented with other datasets to get a more comprehensive picture of front-end production capacity. The September 2024 version of the 300mm Watch dataset is the basis for the analyses presented in this paper.

TechInsights also provides the Semico Fab Database, which is the third dataset contributing to the Network’s overview of the global production landscape (Semico Research, 2024[7]). The production data analyses presented in this paper use the Semico Fab Database Update Summary 2023 as one of the fab data sources.

Desk research

Neither of the datasets are fully complete, correct and accurate. With many tracked fabs globally and a rapidly evolving ecosystem, missing information, coverage biases and inaccuracies can be expected. Moreover, existing datasets are usually designed for other purposes than policy analyses and hence might lack information relevant for policymakers. Therefore, the OECD also carried out desk research to verify, correct and complement the data available from the commercial data sources described above. Desk research includes financial reporting from companies, expert interviews, exchanges with the Network participants and media reporting from varied sources.

Data limitations

When interpreting the figures and analysis presented in this paper, several important data limitations should be taken into account, as they affect the accuracy and comparability of the underlying wafer fabrication data. These limitations arise from inconsistencies across commercial datasets, missing detail on process technologies and materials, incomplete geographic coverage, and uncertainty surrounding future developments.

Process nodes

The feature size1, generally measured in nanometres (nm), is a very rough proxy for the technological advancement or maturity of the chips that a fab can produce. This is therefore an important variable to consider when assessing capability, in particular of logic fabs.

Nevertheless, these types of data present some challenges. For example, when assessing only geometries (density) of process nodes – such as 7nm, 14nm or 28nm process nodes – it becomes evident that there are recurring discrepancies between public information provided by companies collected through desk research and what is reported in the commercial datasets described above. For example, at the time of writing, Samsung’s foundry business lists the following logic process nodes on their website: 3, 4, 5, 7, 8, 14, 28, 70, 90, 130 and 180nm (Samsung, n.d.[16]). However, WFW lists only the following in-production logic process nodes for Samsung’s foundry business: 3, 8, 9, 11, and 28. For comparison, TechInsights’ 300mm Watch lists in-production Samsung’s foundry offerings as 3, 5, 10, 14, 20, 28, 40 and 65nm. GlobalFoundries is another example: The company states they offer 12, 22, 28, 40, 45, 55, 90 and 130nm processes (GlobalFoundries Inc., 2022[17]). WFW does not include the 28, 55 and 130 processes and adds 9nm and 180nm process nodes for GlobalFoundries.

These discrepancies in tracking wafer capacity per process node density extend to individual fabs as well. While SEMI only lists one feature size per fab (often, but not always, the densest feature size a fab is capable of), TechInsights provides the range of feature sizes with rough capacity shares. For instance, the same fab might be recorded as 40nm in SEMI but listed with 40, 65, 90 and 130nm in TechInsights, with estimates of the respective wafer capacity shares. Thus, given the characteristics of the commercial data, there is a tendency to overestimate the capacity of the smallest nodes available in a fab.

These recurring discrepancies can lead to significantly biased results for specific process node sizes. While some of the biases could be mitigated by analysing process nodes in ranges, (e.g. “20-45nm” or “5nm and below”), such an approach would not allow for meaningful insights into the geographic distribution of specific process nodes (e.g. 28nm logic). Because there seems to be no consistent breakdown of capacity by feature size within each fab, it severely restricts the ability to assess substitutability of manufacturing.

Process technologies

For most types of chips, node density (also referred to as feature size) is not the only, and sometimes not even the most relevant, metric. Process nodes can be differentiated by many characteristics beyond the density of the production process.

Foundries often offer special production technologies for their process nodes that are optimised for specific chip types, such as analog, radio frequency (RF), mixed-signal or power semiconductors. For example, on some production lines, GlobalFoundries offers Bipolar-CMOS-DMOS (BCD)2 process technology specifically for the production of power management chips (GlobalFoundries Inc., 2023[18]). Additionally, Table 1 lists the available process technologies for selected process nodes by Tower Semiconductors.

Table 1. Process Technologies at different process nodes from Tower Semiconductors

Process node	Process technology
	SiGe	RF SOI	RFCMOS	Logic	BCD	CIS	SiPho
45 nm		✓		✓			✓
65 nm	✓	✓	✓	✓	✓	✓
130 nm	✓	✓	✓	✓
180 nm	✓	✓	✓	✓	✓	✓	✓
>=250 nm	✓		✓	✓	✓	✓

Note: Different process technologies are only offered for specific nodes.

Source: Based on Tower Semiconductor (n.d.[19])

Unfortunately, neither SEMI nor TechInsights consistently track the variety of production technologies available per process node. To assess the geographic distribution (and substitutability) of production such information is indispensable. For example, if a chip design company is seeking a second source for their power management chip built on a 40nm process with BCD technology, another foundry’s 40nm process optimised for RF applications will be of little use (TSMC, n.d.[20]).

Furthermore, neither of the datasets provide information on capacity distribution by process technology, meaning that wafer starts per month (WSPM) is not broken down by specific process technologies. For instance, even if a fab offers multiple process technologies for mature logic, analog, power, and memory chips, the majority of wafers could still be produced using a single technology, such as BCD.

Currently, publicly available wafer capacity analyses do not address differences in-production technologies and instead focus on comparing node densities.

Semiconductor material

While silicon wafers (Si) continue to be the dominant material for semiconductor production, other wafer materials, such as GaN and silicon-carbide (SiC) vastly outperform silicon in specific applications, such as for power and RF chips (Ma and Gu, 2021[21]).

Fabs often have multiple production lines for different wafer materials, such as GaN, SiC or silicon-germanium (SiGe). However, based on the data in WFW and TechInsights, it is only possible to determine whether a fab can use different types of wafers. The data do not indicate the share of wafer output by each wafer material.3

Geographic coverage

In the current geopolitical context, with increasing concerns about excess capacity in legacy chip production, certain companies have little incentive to clearly communicate technological capabilities, production capacities and utilization rates. This is, for example, the case of Chinese Integrated Device Manufacturers (IDMs) and foundries. The availability of data on production capacity is particularly challenging in the case of China. Thus, data about technological capabilities and manufacturing capacity of fabs in China should be interpreted with caution. For example, there have been instances of commercial datasets being updated only after public media reported about new investments in Chinese fabs (King and Debby, 2023[22]). Consequently, it is likely that actual wafer fabrication capacity in China is higher than estimated in this paper.

Developments in semiconductor technology

Developments in semiconductor technology can add complexity to the data and introduce biases. For example, the rise of advanced packaging is likely to result in further diversification in semiconductor production. There are now application specific approaches for wafer fabrication as well as packaging, with foundries offering complete solutions, covering wafer fabrication and packaging. Therefore, assessing substitutability must extend to beyond front-end processes. If a chip design is based on a foundry’s process node and an advanced packaging process, it creates a stronger customer-supplier lock-in. This benefits the foundry, which is why most leading foundries are evolving their business models to become “solution providers” (Trendforce, 2024[23]). Consequently, comparing wafer fabrication capabilities and capacities alone is becoming increasingly inadequate and necessitates further work on the measurement of back-end manufacturing.

Uncertainty of upcoming fabs

There is uncertainty about projected production capacity in future fabs, with some more likely to materialise than others. Due to changes in economic, technological, and strategic considerations, not all upcoming fabs will come into operation. Plans to expand capacity might be put on hold due to market downturns, and greenfield investments are sometimes delayed indefinitely. Hence, the reported data used in the analyses presented here may not reflect the latest developments in the dynamic front-end manufacturing fab expansion cycles and should be merely seen as a snapshot in time – September 2025.

The uncertainty surrounding upcoming fabs is evident when comparing fab-level data across different updates from the data providers. Some fabs previously described as having a high likelihood of starting operations are now either on hold or delayed indefinitely. For instance, expansion plans by ams-OSRAM in Kulim, Malaysia, which began construction in 2022, was scaled back in 2024 (Edison Report, 2024[24]). Although the 2023 update reported a high likelihood of operation in the fourth quarter, data recorded since the third quarter of 2024 no longer projects it to become operational in the near future. Similar patterns are observed with data reporting of Intel’s fab in Magdeburg, Germany and Samsung fabs in Pyeongtaek, Korea (Hookway, 2025[25]; Trendforce, 2024[23]).

These and other developments may affect the analyses in section 3, which should be interpreted with these considerations in mind.

Notes

← 1.  Feature size is typically measured by the half-pitch of the smallest metal lines in the chip. It reflects the smallest distance between two identical features (like transistors or interconnects) in the logic circuitry; for NAND flash memory NAND density is increasingly described by the number of layers in 3D NAND architectures; DRAM feature size is measured by the smallest dimension of the memory cell, typically the half-pitch of the storage capacitor or the transistor gate in the memory array.

← 2.  BCD (Bipolar-CMOS-DMOS) is a semiconductor process technology that integrates bipolar transistors, CMOS logic, and DMOS power devices on a single chip, and it is commonly used in applications such as power management ICs, motor drivers and automotive electronics.

← 3.  As an example, WFF only states that Infineon’s new fabs produce SiC- and GaN-based chips but holds no information about the respective shares of wafer capacity.